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  + DSP

  + FPGA

  + ADC

  + Power

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The ADSP-BF561 part contains two Blackfin cores, running at 600MHz. This unique member of the Blackfin family is particularly well suited to the application, as it has two PPI (Parallel Peripheral Interface) ports that can accept streams of pixel data from the ADCs; since BigCam has two ADCs, this works out perfectly.

The DSP connects to a 128MB bank of SDRAM (32-bit wide, running at 120MHz) through its External Bus Interface Unit, and to other devices through SPI. Those "other devices" include:

The digitized image data is read from each PPI by a DMA engine, and streamed into external SDRAM without DSP core involvement. In the future, the data could be streamed into L1/L2 caches inside the DSP instead, and the cores could perform tasks like image compression in real time before sending the data out to SDRAM.

The DSP views the FPGA as a set of memory-mapped devices. Since that memory bus is common with the SDRAM bus, the FPGA can directly interact with the SDRAM by requesting the DSP to relinquish control of the bus (bus request/grant mechanism).