The FPGA performs two main functions in BigCam. Since the DSP lacks any sort of network controller, the FPGA contains a minimal Gigabit Ethernet MAC. The other function is generation of clocks and timing signals for the imaging datapath.

The FPGA connects to DSP's memory bus through its MCIF block. The MCIF can respond to asynchronous reads & writes from the DSP (this is how the FPGA appears as a memory-mapped device in DSP's address space), but it also has the ability to monitor DSP's SDRAM write transactions and issue its own SDRAM read transactions. The latter two are used by the Gigabit Ethernet transmit path.

The Gigabit Ethernet controller is split into transmit and receive sections. Since a camera mostly acts as a transmitter of data, the transmit path is designed for best performance, and the receive path for optimal cost.

Ethernet transmit path can operate in two modes. In the first mode, the DSP defines a memory range for a frame (or a segment of a frame), and then writes the data into this range in SDRAM. If the controller has enough buffer space inside the FPGA, it will capture the writes as they happen to SDRAM and send them directly to the MAC; if not, the memory range will be saved for later and SDRAM read transactions will be issued to read the data from SDRAM.

The second transmit mode is similar to the latter case, except the DSP forces the FPGA to read data from SDRAM. This can be used to transmit previously prepared frames, since the DSP does not need to write the frame after the memory range is defined.

The sensor timings & other clock/timing signals for the imaging path are generated by the Timing Sequence Controller. The TSC block is a microcoded engine with hardware support for 2D loops that can create complex waveform sequences. The architecture of the TSC allows for any and all output signals to be set in a given cycle, and then a wait of an arbitrary number of cycles can be commanded, with 1-cycle resolution. The controller also supports event waits (for instance, for precise synchronization with external timing sources) and 2 levels of hardware, zero-overhead loops.

The last element of the FPGA is the SPI controller. The FPGA loads from a local 2MB Flash; to program this Flash, the DSP uses FPGA's SPI controller and loads the bitstream there.