The power supplies operate entirely from a 5V input. The FPGA and Ethernet PHY both require 1.2V for their high speed logic, the CPU needs a programmable voltage between 0.8 and 1.4V for the core, and all I/O (including SDRAM) runs at 3.3V.
The 3.3V and 1.2V power supplies are provided by Enpirion EN5322QI, a 2A-output converter with an integrated inductor. The programmable core voltage is provided by EP53F8QI, a similar part with 1.5A output current. The voltage is adjustable through a Microchip MCP4162, a SPI-controlled potentiometer placed in the feedback loop of the Enpirion regulator. The DSP can lower its core voltage when it's running at a clock frequency lower than 600MHz, and significantly reduce the power consumption.
The sensor requires a number of power supplies: VDDR (reset), VDDA (array), VDD (logic) and GNDAB (anti-blooming drain). All of these are driven by a quad 12-bit DAC, driving four high output current amplifiers configured as buffers. In addition, the sensor's bias currents can be controlled through a Microchip quad potentiometer. This, in conjunction with the image sensor's flexibility (all timing control pins are exposed - there is no internal timing generator), allows interesting future modes of operation like HDR in a single exposure through tuning the VDDR/VDDAB, or soft reset operation.
(c) 2011 Stanislaw Skowronek
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